1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a process for improving a salicide process while simultaneously improving the reliability of the integrated circuit.
2. Description of the Relevant Art
MOS transistors may be broadly characterized as either short channel or long channel devices. In an ideal long channel device, the sub-threshold current is independent of the drain voltage, the threshold voltage is independent of the channel length and the transistor biasing, and the drain current in the saturation region is independent of the drain voltage. It will be appreciated that these characteristics of long channel devices are desirable from a manufacturing and circuit design perspective because of their tendency to minimize subthreshold currents and threshold voltage variation among transistors of varying dimensions. In contrast, short channel devices are characterized by a subthreshold current that varies with drain voltage, a threshold voltage that varies with channel length and biasing conditions, and a failure of current saturation in the saturation region. The minimum channel length which can be expected to result in long channel subthreshold behavior for a given set of process parameters varies with the junction depth x.sub.j as indicated by the equation: EQU L.sub.min =.gamma.'x.sub.j.sup.1/3 Eq. 1
where .gamma.'=0.4[t.sub.ox (W.sub.s +W.sub.d).sup.2 ].sup.1/3 and t.sub.ox is the thickness of the gate dieletric and W.sub.s and W.sub.d are the depletion layer widths around the source and drain respectively. See, e.g., S. M. Sze., Physics of Semiconductor Devices pp. 431-86 (John Wiley and Sons, 1981). As indicated by Equation 1, the minimum channel length for long channel operation varies with the cube root of the junction depth (other parameters being equal). As the channel length of MOS transistors has been reduced through advancements in photolithography and other semiconductor processing techniques, the significance of the subthreshold characteristics and the efforts to minimize subthreshold effects have been correspondingly increased. Unfortunately, the conventional methods of forming source/drain regions have proven frustrating for process designers attempting to minimize short channel effects. Typically, source/drain regions are fabricated by an ion implantation technique in which energetic ions of appropriate impurities, or boron are implanted into a single crystal silicon substrate. Even when used in conjunction with a dielectric layer formed on the surface prior to the implantation, the ion implantation process typically results in a junction depth x.sub.j that places a lower limit on the minimum channel device that can be fabricated with long channel characteristics. In addition, processing subsequent to the ion implantation process typically redistributes the ion implantation distributions such that the as implanted junction depth is less than the junction depth that exists at the completion of the fabrication process. Accordingly, efforts to minimize short channel effects in MOS transistors in the submicron range have been greatly constrained by the minimum junction depth x.sub.j typically available with the standard MOS transistor formation process.
In addition to minimizing junction depth, decreasing the resistivity of structures that contact the silicon source/drain regions and the polysilicon gate conductor also increases in significance as the features of integrated circuits continue to shrink. Highly resistive contact structures result in increased capacitive coupling and decreased device performance by increasing the RC time constant of the associated interconnect structure.
The RC time constant of an interconnect structure is expressed in the following form: EQU RC=R.sub.s L.sup.2.epsilon..sub.ox /X.sub.ox (Eq. 2)
where R.sub.s is the interconnect's sheet resistance, L is the length of the interconnect, X.sub.ox is the dielectric thickness underlying the interconnect, and .epsilon..sub.ox is the permittivity of the underlying dielectric, such as silicon dioxide. In order to fabricate dense, high speed MOS devices, Equation 2 illustrates the benefits of minimizing the resistivity R.sub.s as much as possible and this includes minimizing the contact resistance.
One way in which to reduce the resistivity of contacts to the gate conductor is to substitute aluminum for polysilicon because the resistivity of aluminum is considerably lower than that of polysilicon. Unfortunately, the relatively low melting point of aluminum makes the use of aluminum as a gate/interconnect an impossibility if subsequent processing steps involve temperature cycles greater than approximately 500.degree. C. (In addition, using aluminum for the transistor gate does nothing to decrease the resistance of contacts to the source/drain regions.) Aluminum is, therefore, typically used only at the latter stages of integrated circuit fabrication (i.e., after the high temperature cycles such as impurity drive-in and anneal) are completed.
To address the contact resistance problems noted above, silicide structures have been employed. A silicide is a refractory metal-silicon composite typically formed at the upper surface of the silicon structure. Silicides are commonly formed by depositing a refractory metal across the silicon upper surface (for purposes of this application, a refractory metal is a metal having a melting point in excess of approximately 1400.degree. C.). The silicon/metal interface is then heated to react the silicon with the overlying metal to form the silicide. Any unreacted metal portion is then typically removed leaving only the silicide at the upper surface of the silicon. The silicide structure beneficially reduces the resistivity of subsequently formed contacts.
In many conventional processes that employ silicides, however, achieving a uniform resistivity for silicides formed over polysilicon interconnects of varying geometries is difficult. It is theorized that regions of high resistivity polysilicon, in which mobile carriers become easily trapped, exist in the vicinity of the grain boundaries characteristic of polysilicon films. It is further theorized that, as these regions become comparable in size to the overall width of the polysilicon interconnect, insufficient quantities of silicon are available to form high quality silicides. Accordingly, the formation rate and quality of silicides formed on the upper surface of narrow polysilicon interconnects may drop below the formation rate and quality of silicides formed on wider polysilicon structures. Geometry dependent silicide resistivity is undesirable because semiconductor devices and processes are almost universally designed and simulated under the assumption that silicide resistivity, as with most other parameters, will not exhibit a geometric dependence. Accordingly, it is highly desirable to implement a fabrication process that minimizes geometric variations in silicide resistivity.
The most popular refractory metals for use in semiconductor processing include the Group VIII metals or titanium (Ti). The Group VIII metals include cobalt (Co), platinum (Pt), palladium (Pd), and nickel (Ni). The Group VIII metals typically react with underlying silicon at relatively low temperatures, e.g., at 600.degree. C. or less. The Group VIII metals exhibit fairly low resistivity; however, they cannot reduce substantially thick native oxides formed on the silicon-based surface. More specifically, Group VIII metal atoms and silicon atoms cannot interdiffuse across a native oxide having a thickness exceeding, for example, 50 angstroms. Resulting from the shortcomings of Group VIII metals, titanium has been used for its ability to reduce native oxide layers exceeding 50 angstroms. Titanium is the only known refractory metal that can reliably form silicide on both polysilicon and silicon surfaces having naturally occurring native oxides.
The benefits of titanium readily diffusing into underlying silicon is also a detriment, to some extent. Elaborate procedures have been established to prevent excessive interdiffusion not only in the underlying silicon surface, but also into adjacent oxide surfaces. Even though titanium diffusion is carefully controlled using, for example, a two-step anneal sequence, the affinity of titanium and silicon interdiffusion is so extensive that in some instances titanium can "spike" through relatively shallow junctions. It would therefore be desirable to implement a silicide process that addresses the problems of junction spiking without adding elaborate procedures or extensive costs to the manufacturing process.